Articles A200 through A203 covered the historical trajectory, the design space, the state of the practice, and the meta-factory manufacturing prior art for hardware description languages and their surrounding ecosystem. Article A201 specifically identified self-hosted synthesis toolchains as an increasingly reachable research direction, enabled by the maturation of Yosys, nextpnr, and F4PGA into production-adjacent open-source flows. This article addresses the specific concept of a self-hosted silicon compiler as the concrete integration point between the computational side of the reproduction loop that articles A201 and A202 identified.
The phrase self-hosted silicon compiler refers to a system in which the compilation toolchain that turns a hardware description into a device configuration bitstream runs on the hardware that the toolchain produces. The distinction is analogous to the software-compiler tradition in which a language’s own compiler is written in that language, compiled by an earlier bootstrap version, and then capable of compiling itself. The stream-based compilers series of articles A188 through A199 developed this pattern in detail for the software case. The hardware case imposes several additional constraints that the software case does not, principally because hardware description compilation depends on physical device geometries that a programmable-fabric target must be able to represent faithfully.
A silicon compiler in its narrow sense translates a hardware description in a language such as Verilog, VHDL, or one of the embedded-domain-specific-language revival languages, into a device-specific bitstream that programs a field-programmable-gate-array or configures an application-specific-integrated-circuit mask set. The translation runs through several intermediate stages including elaboration, synthesis, technology mapping, place-and-route, and bitstream generation. The traditional industrial flow runs these stages on general-purpose central-processing units, typically x86-64 servers running Microsoft Windows or GNU/Linux, using proprietary tooling from AMD, Intel Altera, Synopsys, Cadence, or Siemens Electronic-Design-Automation.
A self-hosted silicon compiler runs the same translation pipeline on hardware that the compiler itself produces. The strongest form of self-hosting runs the toolchain on a soft processor core implemented in the field-programmable-gate-array fabric that the toolchain also targets. Weaker forms of self-hosting run the toolchain on a hard processor integrated with the target fabric in a system-on-chip package, or on a companion processor that shares the programmable-fabric device in a partitioned configuration.
The distinction matters for two reasons. The first reason is dependency reduction. A system that runs its own compilation toolchain on its own hardware depends neither on a proprietary tool vendor nor on external general-purpose processing hardware. The second reason is the reproduction loop that articles A201 and A202 discussed. A meta-factory that manufactures new field-programmable-gate-array devices must be able to generate appropriate bitstreams for the new devices without external tooling support. Self-hosted silicon compilation provides the computational half of this loop.
The compiler-tradition literature addresses the self-hosting question substantially. A self-hosted compiler is a compiler written in its own source language, compiled by an earlier bootstrap version, and then capable of compiling itself. The bootstrap procedure begins with a minimal initial compiler written in a different language, often assembly or an earlier target of the same compiler tradition. The initial compiler compiles a simpler version of the target compiler. The simpler version compiles a more sophisticated version. Successive iterations converge on a fixed point where the compiler reproduces its own binary from its own source.
The pattern is canonical across Wirth’s Oberon, Rust, Go, and the GNU Compiler Collection. Article A199, the closing article of the stream-based compilers series, developed the fixed-point condition formally as a coalgebraic self-hosting endpoint. The bootstrap sequence provides one specific mechanism for reaching the fixed point, though alternative mechanisms including cross-compilation from an already-hosted compiler also work.
The software bootstrap faces one fundamental security-adjacent concern that the hardware case inherits. Ken Thompson’s Turing Award lecture titled Reflections on Trusting Trust demonstrated that a compiler can be modified to insert malicious code into the binaries it generates without any visible source-level trace. If the modified compiler also inserts the same modification into future versions of itself, the malicious behaviour propagates across successive bootstrap cycles even after the original malicious source is removed.
David A. Wheeler formalised a countermeasure called Diverse Double-Compiling in his two thousand nine work. The procedure compiles the target compiler’s source twice, once with a trusted alternative compiler and once with the untrusted compiler-under-test. If the two resulting binaries are bit-for-bit identical, the source code accurately represents the untrusted binary and no trusting-trust attack has been undetected. The Wheeler procedure applies to software self-hosting directly and to hardware self-hosting in analogous form, though the hardware case requires adaptation of the bit-identical comparison across the analog-and-digital boundary that device fabrication introduces.
The strongest existing demonstration of a self-hosted hardware-and-software computing system is Gabriel Somlo’s Trustworthy Free Libre Linux-Capable Self-Hosting sixty-four-bit RISC-V Computer at Carnegie Mellon University’s Software Engineering Institute. Somlo’s project addresses a specific goal, namely building a free-and-open-source computer from the ground up so that the entire hardware-and-software system’s behaviour is one hundred percent attributable to its fully available hardware-description-language and software sources.
The system architecture consists of several composable components. A Rocket Chip RISC-V processor, which is written in Chisel, provides the central processing unit. LiteX provides the rest of the system-on-chip including memory controllers, peripheral interfaces, and interconnect. The design is deployed on a Lattice ECP5 field-programmable-gate-array board. The bitstream is generated from sources by a fully free-libre toolchain consisting of Yosys for synthesis, Project Trellis for ECP5 bitstream documentation, and nextpnr for place-and-route. The software stack runs Fedora Linux on the RISC-V soft processor.
The self-hosting property that Somlo’s project demonstrates is substantial. The system is capable of recompiling not only its own software including the Linux kernel, the GNU C Library, and the GNU Compiler Collection, but also its own gateware, namely the field-programmable-gate-array bitstream, completely from source code. The recompilation runs on the RISC-V soft processor that the bitstream itself produces. The self-hosting property therefore holds at the source-to-bitstream level even though it does not extend to the physical silicon fabrication of the underlying Lattice ECP5 device.
The silicon boundary is explicit in Somlo’s project design. The programmable-fabric device itself was fabricated by Lattice Semiconductor using proprietary photolithographic processes, foundry equipment, and device masks that Somlo does not control. The self-hosting property holds above the silicon boundary, specifically for everything that is representable as source code that runs on the RISC-V processor or as gateware that runs on the ECP5 fabric. Below the silicon boundary, the device depends on the same proprietary fabrication supply chain that industrial hardware design flows depend on.
The silicon boundary identifies where existing self-hosting technology ends and where substantially harder research directions begin. Above the silicon boundary, the design is representable as source code and compilable by the toolchain that the design itself implements. Below the silicon boundary, the design depends on physical fabrication processes that require substantial industrial infrastructure including photolithographic steppers, chemical vapour deposition equipment, ion implanters, plasma etching systems, and deep-ultraviolet or extreme-ultraviolet light sources. None of these components are representable in any current hardware description language, and none of them can be manufactured by the same hardware description language toolchain that generates the design they will fabricate.
Two distinct research directions approach the silicon boundary from above. The first direction compacts the self-hosting toolchain into the minimum possible implementation that still supports useful hardware description work. The compaction reduces the trust surface, because a smaller toolchain has fewer opportunities for subversion and can be audited more thoroughly. The compaction also reduces the compile-time cost, which matters when the toolchain runs on a soft processor core whose performance is substantially below a general-purpose central processing unit’s.
The second direction targets the fabrication process itself. Research work in electron-beam lithography, maskless lithography, and molecular self-assembly suggests that future fabrication processes might be substantially more representable in description languages than current photolithographic processes are. A hypothetical fabrication process whose setup and control were representable in a hardware description language extension could in principle be generated by the same toolchain that generates the device designs that the fabrication process produces. Article A202 addressed the meta-factory prior art that grounds this research direction in substantial engineering literature.
The silicon boundary therefore represents a current technological limit rather than a fundamental theoretical barrier. Extending the self-hosting property below the silicon boundary requires substantial advances in fabrication technology that are not principally computer-science research directions. The intersection of computer science and semiconductor process engineering that would be required is substantial but not unprecedented, and the meta-factory literature that article A202 covered provides several starting points for the integration work.
The first of the two research directions identified above, namely compact self-hosting toolchains, has several prototype and research artefacts that demonstrate partial progress.
Compact synthesis toolchains. Yosys is substantially more compact than the proprietary industrial toolchains that it competes with. The Yosys source is on the order of several hundred thousand lines of C-plus-plus, which is several orders of magnitude smaller than the multi-million-line codebases that Vivado and Quartus Prime represent. The compactness enables Yosys to run on soft processor cores that would not support proprietary toolchains, which is what enables the Somlo project’s self-hosting property. Further compaction of Yosys or successor synthesis toolchains represents one active research direction.
Minimal-grammar hardware description languages. A hardware description language with a minimal grammar requires a substantially smaller compiler than a language with a rich grammar. Silice, the hardware description language by Sylvain Lefebvre at the National Institute for Research in Digital Science and Technology in France, provides a substantially simpler grammar than Verilog or VHDL while still supporting useful hardware description work. Silice compiles to Verilog and then to Yosys for synthesis, so it does not itself reduce the toolchain footprint, but its grammar suggests that substantially simpler languages are compatible with useful hardware description.
Compact-toolchain-friendly language design. Article A201 identified the streaming compilation discipline that Keleusma demonstrates in its software-target implementation. The Keleusma language, a total functional stream processor that compiles to bytecode for embedded scripting and high-assurance embedded control contexts, implements a compact compilation toolchain whose worst-case memory usage and worst-case execution time are statically bounded at compile time. Adapting the Keleusma compilation discipline to a hardware-target implementation remains an open research question, and its design-in-progress status means that whether the software analysis passes adapt to a hardware description target is not yet established. If the adaptation succeeded, the resulting hardware description language would support a substantially smaller compilation toolchain than current alternatives, which would advance the compact-toolchain research direction.
On-fabric compilation acceleration. Recent research including graphics-processing-unit-accelerated register-transfer-level simulation suggests that substantial parts of the synthesis pipeline are amenable to hardware acceleration. An accelerator core that implemented the most expensive compilation stages in dedicated hardware running on the same field-programmable-gate-array device as the target design would substantially reduce the compile-cycle time that the soft-processor implementation currently imposes. The research direction combines compact toolchain design with domain-specific hardware acceleration.
Bootstrap procedure design. The bootstrap sequence for a self-hosted silicon compiler requires a minimal initial compiler that generates a minimal initial bitstream capable of running a subset of the target hardware description language. The initial bitstream runs a simpler version of the target compiler, which generates a more sophisticated bitstream, and so on until the sequence reaches the fixed point. The design of the minimal initial compiler and the corresponding initial bitstream is the specific research problem that each self-hosted silicon compiler project must solve. Somlo’s project addresses this problem by cross-compilation from an already-hosted GNU toolchain. Somlo references Wheeler’s Diverse Double-Compilation procedure as a related mitigation technique for the underlying trust concern, though the specific integration of Diverse Double-Compilation into the Somlo bootstrap sequence remains a follow-on research direction rather than an implemented component of the current system.
The applications for self-hosted silicon compilation concentrate in specific target contexts where the tooling complexity that the property adds is justified by the specific architectural benefits.
Trust-adjacent computing. The Trusting Trust countermeasure that Wheeler’s Diverse Double-Compilation provides depends on the existence of a fully self-hosted toolchain so that the entire binary state can be reproduced from source without external dependencies. Somlo’s project targets this application principally in its research framing. Applications for trust-adjacent computing include high-assurance systems where the software supply chain must be auditable end to end, and long-term autonomous systems where the operating environment does not provide external tool vendor support.
Educational applications. A self-hosted silicon compiler running on a soft processor core that students can inspect and modify provides a substantially more transparent learning environment than proprietary industrial tools that students cannot audit or extend. The educational context values the source-level attributability of the entire toolchain even when the compile-cycle time is substantially longer than the industrial alternative.
Long-term autonomy contexts. Article A202 discussed the meta-factory prior art for autonomous manufacturing in contexts where external software support cannot be assumed. A self-hosted silicon compiler provides the computational half of the reproduction loop that such systems require. The application is substantially longer-term than the trust-adjacent or educational applications, but the underlying technical requirements are similar, and work that serves the short-term applications directly supports the long-term application as well.
Reproducible builds for hardware. The reproducible-builds movement in software distribution requires that each release binary be reproducible bit-for-bit from its stated source under a specified build environment. Applying the same discipline to hardware description requires a fully self-hosted toolchain whose outputs are bit-for-bit reproducible from source. Somlo’s project demonstrates this property at the source-to-bitstream level above the silicon boundary. The reproducible-hardware-builds community is substantially smaller than the reproducible-software-builds community but serves comparable audit-and-verification goals in hardware distribution.
Article A202 addressed the prior art for meta-factories, namely factories whose primary product is other factories. The article covered von Neumann’s Universal Constructor, the nineteen eighty NASA studies of lunar self-replicating factories, Freitas and Merkle’s two thousand four kinematic self-replicating machines survey, Adrian Bowyer’s RepRap project from two thousand five, and industrial digital-twin meta-factory platforms from Hyundai Motor Group and comparable automotive manufacturers.
A self-hosted silicon compiler provides the computational half of the reproduction loop that these meta-factory prior art traditions address. The meta-factory manufactures the physical devices, including the programmable-fabric target that the compiler runs on and the soft processor core that the compiler targets. The self-hosted silicon compiler generates the bitstreams that program the newly manufactured devices to implement the meta-factory’s next generation of control systems, signal processing, and sensor interfaces. The two components together close the reproduction loop that each alone does not.
The closure does not imply that the loop is complete without substantial additional components. Article A202 identified three additional system components that a complete autonomous manufacturing system requires, namely the physical materials refinery that processes raw inputs into usable feedstocks, the kinematic fabricator that converts digital layouts into physical devices, and a meta-cognitive orchestration layer that manages the entire lifecycle. The self-hosted silicon compiler addresses only the specific integration point between the hardware description tradition and the manufacturing tradition, not the complete autonomous manufacturing system.
The von Neumann probe concept, discussed occasionally in the interstellar-mission speculative literature, provides one motivating application for a fully closed reproduction loop. This article, matching articles A201 and A202, does not develop the interstellar case in detail because the terrestrial applications of self-hosted silicon compilation, including trust-adjacent computing and long-term autonomy contexts, provide substantially more concrete engineering targets than the speculative interstellar case.
The self-hosted silicon compiler represents the specific integration point between the computational and manufacturing halves of the reproduction loop that articles A201 and A202 identified. The concept has substantial existing prior art in the software compiler tradition, which the stream-based compilers series of articles A188 through A199 developed in detail, and substantial current-generation demonstration in Gabriel Somlo’s Trustworthy Free Libre Linux-Capable Self-Hosting sixty-four-bit RISC-V Computer at Carnegie Mellon University’s Software Engineering Institute. Somlo’s project demonstrates the self-hosting property above the silicon boundary, specifically for everything that is representable as source code that runs on the RISC-V soft processor or as gateware that runs on the Lattice ECP5 fabric.
The silicon boundary represents the current technological limit of self-hosting rather than a fundamental theoretical barrier. Extending the property below the silicon boundary requires substantial advances in fabrication technology that are principally semiconductor process engineering research directions rather than computer science research directions. The intersection between the two research communities that extending self-hosting would require is substantial but not unprecedented, and the meta-factory literature that article A202 covered provides several starting points.
Applications for self-hosted silicon compilation concentrate in trust-adjacent computing, educational contexts, long-term autonomous system applications, and reproducible-builds hardware distribution. The applications are substantial enough to justify continued research investment in compact toolchain design, minimal-grammar hardware description languages, on-fabric compilation acceleration, and bootstrap procedure design. The research directions are principally computer science directions, though several of them extend into adjacent engineering disciplines.
Articles A200 through A203 covered the historical trajectory, the design space, and the state of the practice for hardware description languages. Article A202 covered the meta-factory manufacturing prior art. This article completes the four-article thread by identifying the specific integration point between the computational and manufacturing components of the reproduction loop. The thread does not prescribe a specific implementation approach for the integrated system, because the design space supports multiple implementation approaches, but the thread does record that the underlying prior art across both components is substantial enough to justify active research investment in their integration.
Articles A200 and A201 covered the historical trajectory of hardware description languages and the design space that next-generation languages might occupy. This article addresses the third time frame in the same subject, namely the state of the practice as of mid two thousand twenty-six. The question here is not what happened, which A200 answered, nor what could happen, which A201 explored, but what is actually happening in industrial, open-source, and academic hardware design flows.
The article draws on survey data from the annual Wilson Research Group verification study, on vendor toolchain documentation, on ecosystem-maturity indicators in open-source repositories, and on domain-specific adoption reports. The subject resists precise market-share quantification because proprietary hardware design flows do not typically report their language usage, and because adoption patterns vary substantially by geography, industry segment, and company size. The article identifies the qualitative patterns that the available data supports and notes where the data is soft.
The industrial mainstream for digital hardware design remains divided between Verilog and VHDL, with SystemVerilog increasingly absorbing both traditions for new design work. The split between Verilog and VHDL persists along geographic and application lines that were established during the standardisation era. North American commercial designers predominantly use Verilog. European designers, defence contractors, and formal-verification proponents predominantly use VHDL. Within the United States, regional patterns further divide the adoption, with Verilog more prevalent on the West Coast and VHDL more prevalent on the East Coast and in government-adjacent contractor work.
Rough survey estimates from recent industry reports place the combined Verilog and VHDL share of new field-programmable-gate-array design work at approximately eighty-five to ninety percent, with the remaining share distributed across higher-level synthesis targets, embedded-domain-specific-language work, and research prototypes. The specific percentages depend on the sampling methodology and the definition of new design work, so these figures should be treated as directional rather than precise.
SystemVerilog for verification. The twenty twenty-four Siemens Electronic-Design-Automation and Wilson Research Group functional verification study reports that SystemVerilog and the Universal Verification Methodology dominate testbench work in industrial integrated-circuit and application-specific-integrated-circuit projects. The study notes that first-silicon success rates have declined to approximately fourteen percent, the lowest level in two decades, attributed to the growing complexity of system-on-chip architectures, asynchronous clock domains, and safety-critical requirements. The industry response has been increasing adoption of advanced verification methodologies, principally SystemVerilog assertions, the Universal Verification Methodology, and formal verification techniques.
SystemC for system-level modelling. SystemC retains a substantial adoption in system-on-chip design flows where transaction-level modelling is essential. The language is particularly common in mobile-processor and consumer-electronics design work, where the same description must serve both as a simulation model for early software development and as a synthesisable specification for subsequent hardware implementation. SystemC also occupies a substantial share of high-level synthesis flows, where Xilinx Vivado HLS and Siemens Catapult HLS consume SystemC or C-plus-plus source and generate synthesisable register-transfer-level output.
Bluespec in specialised niches. Bluespec SystemVerilog occupies a substantially smaller share than Verilog or VHDL but maintains adoption in specialised niches where the correctness-by-construction argument justifies the tooling investment. Academic processor design work and some high-frequency trading hardware groups report Bluespec adoption. The language’s niche status reflects the trade-off between the tooling ecosystem’s smaller size and the technical advantages of guarded-atomic-action semantics.
The proprietary toolchain vendors for field-programmable-gate-array and application-specific-integrated-circuit design flows concentrate in three principal companies, namely AMD (formerly Xilinx), Intel (formerly Altera), and Synopsys. Cadence and Siemens Electronic-Design-Automation provide substantial complementary tooling. The concentration places a substantial dependency on the toolchain vendors for any industrial hardware design flow.
AMD Vivado. Vivado, originally released by Xilinx in two thousand twelve and inherited by AMD after its two thousand twenty-two acquisition of Xilinx, serves as the primary toolchain for AMD’s Zynq, Kintex, Virtex, and Versal device families. Vivado supports Verilog, SystemVerilog, VHDL, and SystemC source languages, with integrated synthesis, place-and-route, timing analysis, and device programming. The Vivado ML edition adds machine-learning-based optimisation of timing closure and place-and-route decisions.
Intel Quartus Prime. Quartus Prime, the toolchain for the Agilex, Stratix, Arria, Cyclone, and MAX device families, supports the same source languages as Vivado with comparable feature coverage. Intel acquired Altera in two thousand fifteen for approximately seventeen billion United States dollars and subsequently divested a fifty-one percent majority stake to Silver Lake Partners in two thousand twenty-five for approximately eight point seven five billion United States dollars, with Altera returning to its independent Altera Corporation name and Intel retaining a forty-nine percent minority stake. Altera Corporation continues to develop Quartus Prime alongside the device families.
Synopsys Synplify. Synplify Pro provides device-neutral synthesis that targets multiple field-programmable-gate-array device families from a single design flow. Synplify is common in multi-vendor design work where the same design must target devices from more than one vendor, or where the design house wants to maintain vendor independence in its source-code toolchain.
Cadence and Siemens EDA. Cadence and Siemens Electronic-Design-Automation provide complementary tooling in verification, static timing analysis, formal verification, and integrated-circuit physical design. Cadence’s JasperGold formal verification platform and Siemens EDA’s Questa simulation platform are particularly prominent in verification-heavy flows. Both companies also provide their own synthesis and place-and-route tools that compete with the device-vendor tools in specific market segments.
Open-source end-to-end field-programmable-gate-array design flows have matured across the past decade to production-adjacent capability for some device families. The relevant projects form a coordinated ecosystem rather than a monolithic toolchain.
Yosys provides register-transfer-level synthesis, formal-verification-friendly intermediate representations, and substantial device-independent optimisation. The project was started by Claire Wolf in two thousand twelve and has matured into a substantial open-source synthesis toolchain that several downstream projects depend on.
nextpnr provides device-neutral place-and-route, supporting Lattice iCE40, Lattice ECP5, Lattice Nexus, and several other device families through architecture-specific backends. The project is maintained by YosysHQ, which also maintains Yosys.
F4PGA (formerly SymbiFlow) coordinates the open-source tools into a unified vendor-neutral flow for supported device families, principally Lattice iCE40, Lattice ECP5, and selected Xilinx 7-Series devices. The project is associated with CHIPS Alliance, an industry consortium that promotes open-source semiconductor tools.
Project IceStorm provides the reverse-engineered bitstream documentation for Lattice iCE40 devices that Yosys and nextpnr depend on for device-specific place-and-route. The project was principally the work of Claire Wolf and was the first fully open-source end-to-end field-programmable-gate-array toolchain.
The open-source flow delivers end-to-end synthesis from Verilog or Amaranth source to device bitstream without proprietary dependencies for supported device families. Adoption is substantial in academic, hobbyist, and open-hardware contexts. Industrial adoption remains limited principally by device-family coverage gaps. The open-source flow does not currently support AMD’s UltraScale, Versal, or Zynq device families in a production-ready form, which excludes substantial industrial usage.
Article A200 covered the embedded-domain-specific-language revival of the twenty tens. This section records what the individual revival languages have achieved in current adoption.
Chisel. Chisel has achieved substantial adoption in academic and industrial RISC-V design work. The Rocket Chip generator, which produces RISC-V processor implementations, is written in Chisel and is used across several academic and industrial RISC-V projects. SiFive, the commercial RISC-V vendor founded in two thousand fifteen by Krste Asanović, Yunsup Lee, and Andrew Waterman from the University of California Berkeley, the same team that originated Chisel and the RISC-V instruction set architecture, uses Chisel in its core processor design work. Chisel also serves as the source language for the FireSim field-programmable-gate-array-accelerated simulation platform, which several academic groups use for computer architecture research.
Amaranth. Amaranth occupies a substantial share of the hobbyist and open-source field-programmable-gate-array design space. The language’s Python foundation and its integration with the Yosys backend make it the default choice for open-source hardware projects that target Lattice iCE40 and ECP5 devices. Amaranth has produced substantial open-source hardware libraries, including LiteX system-on-chip generators that target open-source soft processors such as VexRiscv and NEORV32.
SpinalHDL. SpinalHDL has achieved adoption in several open-source RISC-V processor projects, notably VexRiscv, which is a commonly used soft processor in open-source field-programmable-gate-array designs. The language’s Scala-based generator paradigm supports substantial parameterisation of processor variants from a single source description.
Clash. Clash occupies a smaller adoption share than the Scala-based or Python-based alternatives, principally because Haskell is less commonly used than Scala or Python in industrial and academic software engineering. The language retains adoption in research groups that work in functional programming and value Haskell’s type system for hardware description work.
MyHDL. MyHDL retains a small but persistent adoption in educational and prototype contexts. The language predates Amaranth and introduced several of the design patterns that Amaranth later adopted. Current adoption is substantially smaller than Amaranth’s because Amaranth’s tighter integration with Yosys and its more active maintenance have displaced MyHDL in much of the Python-based hardware design space.
Formal verification for hardware description has grown from a research-only niche to a substantial component of industrial verification flows across the past decade. The growth is principally driven by the same design-complexity forcing function that motivates the embedded-DSL revival, combined with the declining first-silicon success rates that the Wilson Research Group study documents.
Property checking and model checking. Formal verification tools that consume SystemVerilog assertions or Property Specification Language descriptions have substantial adoption in industrial verification flows. Cadence’s JasperGold, Synopsys VC Formal, and Siemens EDA Questa Formal are the principal industrial-scale platforms. Adoption has grown across the past decade because the increasing complexity of integrated-circuit designs exceeds the capabilities of simulation-only verification flows.
Coq-based hardware description research. Kami and Koika, both developed at the Massachusetts Institute of Technology under Adam Chlipala’s Programming Languages and Verification group, demonstrate formal-verification-integrated hardware description at the source-language level. Kami provides Coq-based modular hardware verification and has been used to verify multicore cache-coherent systems. Koika provides a Bluespec-inspired rule-based hardware description with a formally verified compiler to gates. Both projects remain principally academic at the time of writing, with industrial adoption limited to projects that prioritise correctness proofs over tooling ecosystem size.
Adoption trajectory. The Wilson Research Group study reports that formal verification adoption has grown from approximately thirty percent of industrial verification projects in two thousand fourteen to approximately sixty percent in two thousand twenty-four. The specific percentages vary across industry segments, with safety-critical automotive and aerospace segments reporting substantially higher adoption than consumer-electronics segments.
Several hardware description languages that articles A200 and A201 did not substantively cover occupy specific niches in the current landscape.
Silice. Silice is an open-source hardware description language developed by Sylvain Lefebvre at the National Institute for Research in Digital Science and Technology in France. The language provides a C-like syntax that compiles to Verilog and integrates with the open-source Yosys and nextpnr toolchain. Silice is particularly notable for its demonstration corpus, which includes implementations of Doom and Quake level renderers running on low-cost Lattice ECP5 devices. The language occupies a niche in research and hobbyist work where higher-level abstraction than Verilog combined with open-source toolchain compatibility is desired.
DFHDL. DFHDL, also known as DFiant HDL, is a Scala-based hardware description language developed by the DFiantHDL organisation. The language distinguishes itself from Chisel and SpinalHDL by providing multiple abstraction levels in a single source form, including dataflow, register-transfer, and event-driven abstractions. The dataflow abstraction supports timing-agnostic and device-agnostic hardware description that compiles to platform-specific implementations. DFHDL occupies a research niche at the time of writing but demonstrates a design point that combines multiple abstraction levels in a way that none of Verilog, VHDL, Chisel, or Amaranth currently matches.
LiteX and Migen family. LiteX is a system-on-chip generator framework built on Migen and Amaranth. It provides substantial libraries of pre-designed peripherals, memory controllers, and soft processor cores that Amaranth-based projects can compose into complete system-on-chip designs. LiteX has achieved substantial adoption in academic and open-source hardware projects, particularly for integration with soft processor cores such as VexRiscv and NEORV32.
Migen. Migen, the predecessor to Amaranth, retains some adoption in legacy projects that have not migrated to Amaranth. The Migen ecosystem has substantially shifted to Amaranth over the past several years, so current adoption is principally in maintenance mode rather than in active new development.
PyMTL and MyHDL family. PyMTL, developed at Cornell University, provides a Python-based hardware description and simulation framework that targets academic computer architecture research. The framework has maintained adoption in academic contexts where integration with Python-based analysis tools is valued. Adoption outside the originating academic groups is limited.
Adoption patterns vary substantially across industry segments. Recording the specific patterns by domain identifies where each hardware description language occupies its principal niche.
Automotive and aerospace. Safety-critical automotive and aerospace design work predominantly uses VHDL and SystemVerilog with substantial formal verification integration. The verification-methodology adoption in these segments exceeds the industry average, principally because the first-silicon success requirements are substantially more stringent than in consumer segments. Chisel and Amaranth have some adoption in research and prototype work but have not achieved production adoption in these segments.
Consumer electronics and mobile. Consumer electronics and mobile processor design predominantly uses Verilog and SystemVerilog with SystemC-based transaction-level modelling for early software development. The verification-methodology adoption in these segments is substantial but somewhat behind the safety-critical segments, reflecting the different first-silicon success requirements.
RISC-V processor design. RISC-V processor design has substantial adoption of Chisel and SpinalHDL alongside traditional Verilog and SystemVerilog work. The RISC-V ecosystem’s academic origins and its close integration with the Berkeley Par Lab where Chisel was developed have established the embedded-DSL revival languages in this segment to a greater extent than in other industrial segments.
Academic computer architecture. Academic computer architecture research uses a diverse mix of hardware description languages, with Chisel, Bluespec SystemVerilog, PyMTL, and Kami and Koika all occupying substantial shares of the academic project space. The academic segment has adopted the embedded-DSL revival languages substantially earlier than industrial segments, principally because academic projects prioritise design elegance and generator flexibility over tooling ecosystem maturity.
Hobbyist and open-source hardware. Hobbyist and open-source hardware projects predominantly use Amaranth, Verilog, and Silice with the open-source Yosys and nextpnr toolchain. This segment has the highest adoption of open-source-first design flows because proprietary toolchains represent a substantial cost and dependency that hobbyist projects cannot easily justify.
The overall trajectory across the past decade shows several persistent patterns. The traditional Verilog and VHDL mainstream has proven remarkably durable, with SystemVerilog gradually absorbing both traditions for new design work. The embedded-DSL revival languages have achieved substantial adoption in academic and open-source contexts, but have not displaced Verilog and VHDL in industrial mainstream flows. Formal verification has grown substantially across the same period, principally driven by the declining first-silicon success rates and the increasing complexity of system-on-chip designs. Open-source toolchains have matured into production-adjacent capability for some device families, particularly Lattice iCE40 and ECP5, but have not achieved device-family coverage sufficient to displace proprietary toolchains for most industrial work.
The most substantial recent adoption shift is the integration of formal verification methodologies into industrial verification flows. The Wilson Research Group study’s reported growth from approximately thirty percent to approximately sixty percent formal-verification adoption over a decade represents a substantial industry response to the design-complexity forcing function that articles A200 and A201 discussed. The trajectory suggests that formal verification integration will continue to grow across the coming decade, with increasing pressure on hardware description languages that do not support source-language-level formal verification.
The most substantial open question for the coming decade is whether any of the embedded-DSL revival languages or the formal-verification-integrated research languages will achieve industrial mainstream adoption, or whether the mainstream will remain divided between Verilog and VHDL with SystemVerilog extensions for several more decades. The historical record covered in article A200 suggests that mainstream displacement requires substantial industrial commitment and takes several decades to complete, so significant mainstream shifts in the coming decade appear unlikely absent substantial external forcing functions.
The state of the practice in hardware description languages as of mid two thousand twenty-six shows a persistent industrial mainstream of Verilog and VHDL with SystemVerilog absorbing new design work. Formal verification adoption has grown substantially across the past decade, principally driven by declining first-silicon success rates. The embedded-domain-specific-language revival languages, including Chisel, Amaranth, SpinalHDL, and Clash, have achieved substantial adoption in academic, open-source, and some research-adjacent industrial contexts, but have not displaced the traditional mainstream. Open-source toolchains, principally Yosys, nextpnr, and F4PGA, have matured into production-adjacent capability for some device families but have not achieved device-family coverage sufficient to displace proprietary toolchains for most industrial work.
The adoption trajectory across the coming decade appears principally shaped by formal verification integration and by open-source toolchain device-family expansion. Mainstream displacement of Verilog and VHDL by any of the embedded-DSL revival languages appears unlikely absent substantial external forcing functions. Articles A200 and A201 covered the historical and design-space dimensions of this subject. This article completes the three-time-frame survey by recording the state of the practice that the historical trajectory has produced and the design space must engage with.
Article A200 walked the historical trajectory of hardware description languages across five decades and closed on the observation that each successive wave appeared in response to a specific abstraction gap that prior languages left open at the new scale of integration. This article treats the design space that the next wave occupies. The question is not which specific language will succeed Verilog and VHDL in industrial mainstream flows, because the standardisation-era languages have proven remarkably durable. The question is which design levers remain under-exploited in existing hardware description tradition, and what a hardware description language that combined those levers would look like.
This article is a design-space survey. It identifies pain points in current industrial hardware description flows, records what the recent next-generation hardware description languages have addressed, and examines several further design levers drawn from adjacent programming-language traditions. It closes with a section on self-hosted synthesis toolchains, where the open-source Yosys and nextpnr projects have established production-adjacent precedent, and a brief closer on cross-domain description languages that compose hardware description with mechanical, thermal, and system-level modelling.
Four persistent pain points appear in industrial Verilog and VHDL design flows. Each represents a specific verification gap that the existing hardware description languages close inadequately or not at all.
Pipeline timing verification. A designer who manually balances a pipeline must count clock cycles across each sequential stage and ensure that propagation delays do not violate setup and hold times. The industrial practice uses static timing analysis tools that run after the synthesis stage. This places the timing feedback at the wrong point in the design cycle, because a synthesis run for a substantial field-programmable-gate-array design takes tens of minutes to several hours. Timing violations discovered at this point require substantial source-level rework.
Clock domain crossing. Modern system-on-chip designs contain multiple clock domains, and data that crosses from one domain to another must pass through synchroniser circuits to avoid metastability. Clock-domain-crossing bugs manifest as setup and hold time violations of flip-flops, jitter due to unpredictable delays, and functional issues arising from convergence and divergence of crossover paths. Standard Verilog and VHDL do not express the domain of a signal in the type system, so crossing errors are verified by external static analysis tools rather than by the language itself.
Area budget verification. An industrial hardware designer who writes a complex Verilog module does not know in advance how many look-up tables, flip-flops, and block random-access-memory blocks the synthesised implementation will require. The synthesis tool reports the actual usage after a long synthesis run, and designs that exceed the target device’s available resources require source-level restructuring and another synthesis cycle. The compile-then-discover pattern is particularly costly for educational and prototype work where compile-cycle time dominates the total design effort.
Deadlock and livelock verification. Complex finite-state machines in Verilog and VHDL can enter unmapped states or loop without producing output signal transitions, particularly when concurrent processes interact through shared handshaking protocols. The verification of deadlock freedom uses external formal-verification tools built on model checking or symbolic execution. The languages themselves do not prevent the class of bugs that these tools diagnose.
Article A200 recorded the embedded-domain-specific-language revival that began in the early twenty tens. The revival languages, notably Chisel, SpinalHDL, Amaranth, and Clash, address several of the pain points identified above, though not uniformly and not completely.
The Scala-based languages,
Chisel and SpinalHDL,
address
generator-based design
by
allowing
a
single parameterised description
to
produce
many
concrete circuit instances.
A designer
who
requires
a bank of
sixteen
functionally identical
memory controllers
can
write
one
parameterised module
in Chisel
and
instantiate it
sixteen times
at
elaboration time.
The standardisation-era languages
support
a
weaker form of
parameterisation
through
Verilog’s generate
construct
and
VHDL’s generic mechanism,
but
neither
matches
the full expressive power
of
Scala’s type system
for
compile-time metaprogramming.
Amaranth addresses integration with modern software-engineering workflows by embedding hardware description as a Python library. The Python ecosystem’s package management, version control tooling, and continuous-integration infrastructure apply without adaptation. Amaranth uses Yosys as its synthesis backend, which enables open-source end-to-end design flows for supported field-programmable-gate-array targets.
Clash addresses type-system expressiveness by embedding hardware description in Haskell. Circuit descriptions in Clash inherit Haskell’s type-inference and higher-kinded types, which allow the compiler to detect a substantial class of type errors before synthesis proceeds.
None of the embedded-DSL revival languages address pipeline timing verification at the source-language level. None of them express clock-domain membership in the type system in a form that eliminates the need for external clock-domain-crossing analysis. None of them provide a statically-computed area-budget bound that would allow a designer to detect resource overrun without running the synthesis backend. None of them provide static deadlock and livelock verification. The revival narrowed the abstraction gap but did not close it.
Several design levers that adjacent programming-language traditions have developed remain under-exploited in existing hardware description languages. This section examines four levers and notes where each has been demonstrated in research or prototype systems.
Static worst-case execution time analysis. The worst-case execution time of a program is the longest time that its execution can take under any input. Static worst-case execution time analysis computes an upper bound on this time from source-language control-flow analysis, without executing the program. The technique was developed principally for real-time software and is surveyed by Wilhelm and colleagues. Applied to hardware description, a worst-case execution time computed in clock cycles per stage gives a compile-time timing bound that the designer can verify before the synthesis backend runs. The Keleusma language, a total functional stream processor that compiles to bytecode for embedded scripting and high-assurance embedded control contexts, implements static worst-case execution time analysis at module load and reports the bound in its verification pass. The technique is not inherently tied to software targets. A hardware description language that adopted the same verification pass would produce a per-module timing bound that static timing analysis currently reports only after synthesis.
Totality and productivity as
type-system properties.
The distinction between
functions
that
must
terminate
and
functions
that
must
produce output continuously
originates in
Turner’s total functional programming manifesto
and
was
formalised
through
Rutten’s universal-coalgebra treatment
and
his
subsequent stream-calculus work,
which
together
supply
the mathematical foundation
for
productivity
as
the coinductive dual
of termination.
Article A193
in the compilers series
developed
this framework
in detail.
A hardware description language
that
enforced
totality
on
combinational blocks
and
productivity
on
sequential blocks
at
the type-system level
would
statically
rule out
the deadlock
and livelock
patterns
that
external verification tools
currently diagnose.
Keleusma
categorises
functions
into
three classes,
namely
the atomic total fn category,
the non-atomic total yield category,
and
the productive divergent loop category,
which
maps
directly
onto
the combinational,
sequential,
and streaming
distinctions
in
hardware description.
The
Kami framework
at MIT
demonstrates
a
Coq-based
hardware description language
whose type system
carries
formally verified
correctness properties
into
the compiled circuit.
The Koika language,
also from MIT,
provides
a
formally verified compiler
from
a Bluespec-inspired
rule-based
hardware description
into
gates,
with
machine-checked proofs
that
the semantics
compose
with
one-rule-at-a-time execution.
Both
Kami and Koika
demonstrate
that
formal-methods integration
at
the type-system level
is
feasible
for
hardware description
and
not
limited to
software targets.
Coroutine primitives for
clock-domain crossing.
Clock-domain crossing
is
usually described
in
Verilog and VHDL
through
handshaking protocols
that
the designer
implements
manually.
The pattern
lends itself
to
higher-level
description
under
coroutine
semantics,
where
a
data producer
in one clock domain
and
a
data consumer
in another clock domain
exchange
typed values
through
a
bounded buffer
whose
capacity
is
statically known.
Keleusma
uses
a
strict coroutine model
with
typed
yield and resume primitives
for
host-driven stream processing
in
its
software runtime.
Applied
to
hardware description,
the same
primitives
would express
clock-domain-crossing protocols
in
a form
that
the type system
verifies
directly,
without
requiring
external
clock-domain-crossing analysis.
The
pragmatic formal verification methodology
that
industry practice
currently uses
would
correspondingly
become
redundant
for
languages
that
enforced
this discipline.
Static memory footprint analysis. The area-budget verification gap identified above maps naturally onto static memory-footprint analysis in the software context. Keleusma implements static worst-case memory usage analysis that reports the required arena capacity in bytes at module load, without executing the program. The analog in hardware description would report the required look-up table count, flip-flop count, and block random-access-memory blocks before the synthesis backend runs. The information is in principle computable from the source description because the synthesis tool computes essentially the same information during its elaboration phase. Making the computation part of the type-checking pass rather than part of the synthesis backend would shorten the compile-cycle time for area-budget verification by orders of magnitude.
Composition. The four levers above compose. A hardware description language that adopted all four would statically verify timing bounds, combinational totality, sequential productivity, clock-domain-crossing protocols, and area budgets at the type-checking pass, before the synthesis backend runs. The design would resemble a Rust-and-Bluespec cross-breed, retaining the type-system expressiveness of functional programming languages while compiling to deterministic hardware descriptions. No existing hardware description language implements all four levers in their strongest form. Keleusma implements software-target analogs of three of the four, and its design-in-progress status means that whether its analysis passes can be adapted to a hardware-target implementation remains an open question.
The industrial hardware synthesis flow depends on substantial proprietary tooling. AMD Vivado, Intel Quartus, and Synopsys Synplify occupy the industrial mainstream for their respective target device families. The proprietary tools represent a substantial dependency for any long-term autonomous system that must generate its own hardware designs without external software support.
Open-source alternatives have matured over the past decade to production-adjacent capability for some device families. The relevant projects are Yosys for register-transfer-level synthesis, nextpnr for place-and-route, and F4PGA, formerly known as SymbiFlow, which coordinates the tools into a unified vendor-neutral flow. The current F4PGA flow supports selected Lattice and Xilinx 7-Series device families, with ongoing work on additional targets. For supported device families, the open-source flow delivers end-to-end synthesis from Verilog or Amaranth source to device bitstream without proprietary dependencies.
A self-hosted synthesis toolchain would extend this precedent by running the toolchain itself on the hardware that the toolchain synthesises. The concept is analogous to a self-hosted software compiler that compiles its own source. Current Yosys and nextpnr run on general-purpose central-processing units rather than on the field-programmable-gate-array fabric that they target, so the current state is open-source but not self-hosted in the strict compiler-tradition sense.
Two research directions approach the strict self-hosting endpoint. The first implements a compact synthesis toolchain in a hardware description language itself, such that the toolchain can be synthesised onto the field-programmable-gate-array alongside the target design. The second implements a hardware description language whose compilation output is directly executable by a programmable interconnect without a separate synthesis stage. Neither direction has produced a production-adjacent artefact at the time of writing, though the underlying technology is mature enough that prototype work is within reach for academic and open-source research groups.
The applicability of a self-hosted synthesis toolchain is narrow in mainstream industrial contexts, where the compile-cycle time saved does not justify the tooling complexity added. The applicability is substantial in long-term autonomous system contexts where external software support cannot be assumed, and in educational contexts where the tooling stack is itself the object of study. The von Neumann self-replicating machine concept, occasionally discussed in the interstellar-mission speculative literature, depends on self-hosted synthesis capability among several other essential autonomous-manufacturing capabilities. This article does not develop the interstellar case in detail because the practical applications for self-hosted synthesis are substantially closer to present-day engineering.
The final design lever that this article examines sits outside the traditional hardware description language scope. A complete electronic system description must model not only the digital logic but also the analog behaviour, the thermal characteristics, the mechanical packaging, and the system-level requirements that the design must satisfy. Cross-domain description languages attempt to represent some or all of these concerns in a unified source form.
SysML v2. The Systems Modeling Language version 2, approved in beta form by the Object Management Group in July of two thousand twenty-three, introduces a textual notation for system architecture description alongside the graphical notation that version one supported. The textual syntax enables version-control workflows, code review, and programmatic generation of system models that graphical-only tools did not support. SysML v2 represents system components, their attributes, and the connections between them. A hardware description language that integrated with SysML v2 would place its digital logic modules in a larger system context that included mechanical, thermal, and requirements constraints.
Modelica. The Modelica language, developed by the Modelica Association, provides an object-oriented declarative language for multi-domain physical modelling. Modelica descriptions represent mechanical, electrical, thermal, hydraulic, and control subcomponents in a unified form that supports differential-equation-based simulation. The OpenModelica open-source implementation provides industrial-adjacent tooling for Modelica-based system simulation. Combined with a hardware description language, Modelica would provide the analog and thermal context that the digital design operates within.
Constructive geometry languages. A complete electronic system description must also represent physical geometry for manufacturing. OpenSCAD and CadQuery provide textual representations of three-dimensional geometry that support programmatic generation of computer-aided-design output. A hardware description language that integrated with these tools would generate mechanical enclosures and circuit-board layouts alongside the digital logic.
The composition of these three description languages with a next-generation hardware description language remains an open research question. No existing system-level tool integrates digital hardware description, multi-domain physical modelling, and constructive geometry into a single type-checked source form. The technology to build such an integration is available in principle, but the standardisation across domain boundaries that would enable industrial adoption does not yet exist.
The design space for next-generation hardware description languages contains several under-exploited levers drawn from adjacent programming-language traditions. Static worst-case execution time analysis, type-system encoding of totality and productivity, coroutine primitives for clock-domain crossing, and static area budget analysis each address a persistent pain point in current industrial flows. None of them is speculative. Each has been demonstrated in software targets by existing languages, including Keleusma as a design-in-progress example that implements software-target analogs of three of the four.
Self-hosted synthesis toolchains represent a narrower but increasingly reachable research direction, enabled by the maturation of Yosys and nextpnr into production-adjacent open-source flows. Cross-domain description languages that compose hardware description with system-level requirements, multi-domain physical simulation, and constructive geometry remain an open research question whose standardisation status lags behind the individual component languages.
The article A200 observed that each historical wave of hardware description languages appeared in response to a specific abstraction gap. The gap that the next wave appears positioned to close combines type-system integration with formal verification at the source-language level, and open-source end-to-end synthesis flows whose production-adjacent capability now approaches the industrial mainstream for some device families. Whether a single language will combine these design levers into a consolidated next-generation hardware description language, or whether the design space will remain populated by multiple partial-solution languages, is a question that the current decade will answer.
Hardware description languages occupy an unusual position in the taxonomy of programming languages. They are compiled by tools called synthesisers rather than by compilers, their output is not a program but a circuit described as a netlist of gates and wires, and their execution semantics are defined in terms of concurrent signal propagation rather than sequential instruction dispatch. The languages in this family form a coherent tradition that runs from academic prototypes in the nineteen seventies through commercial standardisation in the nineteen eighties and nineteen nineties to a modern embedded-domain-specific-language revival that began in the twenty tens and continues into the present.
This article walks the history in one pass because the total number of languages that warrant serious historical treatment is modest, on the order of two dozen, and the tradition groups naturally into three overlapping eras that share architectural DNA across their transitions. The three eras are the academic prototypes from approximately nineteen seventy to nineteen eighty-four, the commercial standardisation era from nineteen eighty-four to approximately two thousand ten, and the embedded-domain-specific-language revival that continues from approximately two thousand ten into the present.
The article is descriptive rather than prescriptive. It records what happened, identifies the design-complexity forcing function that motivated each successive wave, and closes with observations about where the space appears to be going.
The pre-hardware-description-language era of digital design worked at the gate and netlist level. A designer drew a schematic that listed gates, flip-flops, and wires, and the schematic was fabricated directly into integrated circuits. This approach scaled to the small-scale-integration and medium-scale-integration levels of the nineteen sixties and early nineteen seventies, where a full chip might contain a few thousand transistors and a manageable number of gates.
The forcing function that motivated the introduction of hardware description languages was the transition from medium-scale integration to large-scale integration and very-large-scale integration across the nineteen seventies. Transistor count per chip grew according to Moore’s Law, which Gordon Moore formulated in nineteen sixty-five and revised in nineteen seventy-five, namely
\[N(t) = N_0 \cdot 2^{t / T},\]where $N(t)$ is the transistor count per chip at time $t$, $N_0$ is the initial count, and $T$ is the doubling period, approximately eighteen to twenty-four months. As transistor counts per chip crossed the ten thousand and later the hundred thousand thresholds, manual schematic capture became impractical. A designer could no longer draw every gate by hand. The abstraction layer had to move up to match the growth in chip complexity.
The design-complexity forcing function repeats at each subsequent wave in the history. Every major hardware description language introduced between nineteen seventy and the present appeared in response to a specific abstraction gap that prior languages did not close. The abstraction gap in the seventies was gate-level to register-transfer-level. The gap in the nineteen eighties was register-transfer-level to behavioural. The gap in the two thousands was behavioural to transaction-level and system-level. The gap in the twenty tens was system-level to generator-and-parameterised design. Each language that this article treats sits at one of these transitions.
The academic era produced several hardware description languages that established the vocabulary and the design patterns that later commercial languages would inherit. None of the languages in this era achieved widespread industrial adoption in their original form, but they contributed essential architectural ideas to the languages that did achieve it.
Instruction Set Processor Specifications (ISPS). ISPS was developed at Carnegie Mellon University in the mid nineteen seventies under the DEC PDP-eleven and PDP-ten architecture-description work of Mario Barbacci and colleagues. The language targeted the description of processor instruction sets and their behaviour at the register-transfer level. ISPS influenced the later processor-description tradition that appears in GNU Superoptimizer, in the ARM Architecture Description Language, and in the LLVM target-description files. It did not directly influence the general-purpose hardware description language family that this article principally treats, but it belongs in the historical record because it established the pattern of using a formal language to describe hardware behaviour.
KARL. KARL, the KAiserslautern Register-transfer Language, was developed by Reiner Hartenstein and his students at the Technical University of Kaiserslautern across the nineteen seventies and nineteen eighties. KARL was one of the first hardware description languages to receive a full formal semantics and a working simulator. Its influence on subsequent European hardware description work was substantial, though it did not achieve American commercial adoption.
ELLA. ELLA was developed at the Royal Signals and Radar Establishment in the United Kingdom across the nineteen seventies and nineteen eighties. It was used for British defence hardware description into the nineteen nineties and had a small but persistent user community that outlasted its official maintenance.
Silvar-Lisco HHDL, CDL, and MetaHDL. Several commercial and academic prototypes appeared in the same period under various acronyms. Most did not survive into the standardisation era. The historical record tends to subsume them under the broader category of pre-Verilog academic hardware description languages, and this article follows that convention.
The academic era established several patterns that carried forward. The register-transfer level as the natural abstraction between behavioural description and gate-level implementation came from this era. The distinction between combinational and sequential blocks came from this era. The event-driven simulation semantics that all subsequent hardware description languages inherit came from this era. The academic prototypes did not achieve industrial adoption because none of them offered a sufficiently attractive combination of language ergonomics, simulator performance, and industrial tooling. The commercial standardisation era that followed would supply all three.
The standardisation era begins with the parallel emergence of Verilog and VHDL in the mid nineteen eighties and continues through their IEEE standardisation in the mid nineteen nineties into the SystemVerilog and SystemC extensions of the two thousands. The two dominant languages of this era, Verilog and VHDL, have coexisted for four decades and now support essentially the same industrial design flows with different syntactic conventions.
Verilog. Verilog was developed between late nineteen eighty-three and early nineteen eighty-four by Prabhu Goel, Phil Moorby, and Chi-Lai Huang at Automated Integrated Design Systems, the company that renamed itself Gateway Design Automation in nineteen eighty-five. Moorby wrote the first Verilog simulator, which came to market in early nineteen eighty-five, and the faster Verilog-XL simulator followed in nineteen eighty-seven. Cadence Design Systems acquired Gateway in nineteen ninety and released the Verilog language definition to Open Verilog International, an industry consortium, in nineteen ninety-one. The Institute of Electrical and Electronics Engineers subsequently standardised the language as IEEE 1364 in nineteen ninety-five. The 1364 standard was revised in two thousand one and two thousand five.
Verilog’s design
prioritised
simulator throughput
and
implementation simplicity.
The syntax
resembles
the C programming language
at
the statement level,
with
concurrent always blocks
substituting
for
sequential function calls.
The language
succeeded
commercially
because
Gateway
had
a working simulator
in nineteen eighty-four
that
outperformed
academic simulators
by
substantial margins,
and
because
the language
was
straightforward enough
that
digital designers
who had been
working
at
the gate level
could learn it
in
a few weeks.
VHDL. VHDL, the VHSIC Hardware Description Language, was developed under the Very High Speed Integrated Circuits program of the United States Department of Defense. The VHSIC program itself began in nineteen eighty, and the VHDL-specific work started under United States Air Force contract F33615-83-C-1003 in nineteen eighty-three. The development team comprised Intermetrics as the prime contractor and language experts, Texas Instruments as the chip-design experts, and International Business Machines as the computer-system experts. At the end of the program in March of nineteen eighty-six, the Institute of Electrical and Electronics Engineers took over standardisation through the VHDL Analysis and Standardization Group, and IEEE 1076 was released in nineteen eighty-seven. The VHSIC program had a substantially larger budget than Verilog’s commercial origins, and VHDL’s design reflects the defence-contracting requirements of its sponsor. The language supports strict type checking, package-based modularity, and formal configuration management that Verilog does not match without substantial extensions.
VHDL’s syntax resembles Ada at the statement level, which is unsurprising given that Ada was the DoD programming language of the same era. The language achieved industrial adoption through DoD contracting requirements that mandated VHDL descriptions for defence electronics, and through European standardisation efforts that preferred VHDL over Verilog for similar reasons of formal rigour.
The Verilog-and-VHDL split divided the industrial hardware design community along geographic and application lines. North American commercial designers predominantly used Verilog. European designers, defence contractors, and formal-verification proponents predominantly used VHDL. The split persisted for two decades and is only now receding as SystemVerilog increasingly absorbs both traditions.
SystemVerilog. SystemVerilog extended Verilog with verification and design features that industrial users had accumulated by the late nineteen nineties. Accellera, the industry consortium that manages hardware design standards, released the initial SystemVerilog specification in two thousand two, and IEEE standardised the language as IEEE 1800 in two thousand five. SystemVerilog added strong data types, object-oriented classes for verification, assertion syntax, and interface constructs that factored common Verilog boilerplate into reusable modules.
SystemVerilog Assertions, often abbreviated as SVA, provided a formal property specification syntax for temporal assertions that industrial designers could embed in their Verilog code. The Universal Verification Methodology, UVM, built on SystemVerilog’s object-oriented features to provide a standard verification testbench framework. Both SVA and UVM are now industry standard for verification-heavy design flows.
SystemC. SystemC originated at Synopsys in nineteen ninety-nine as a C-plus-plus class library for hardware modelling at the transaction level. The Open SystemC Initiative, OSCI, formed in two thousand as an independent consortium to develop and promote the language, and released version 2.0 in two thousand two. IEEE standardised SystemC as IEEE 1666 in two thousand five. Accellera and OSCI subsequently merged in December of two thousand eleven as Accellera Systems Initiative. SystemC targeted system-level design and software-hardware co-design, where the same description could serve both as a simulation model for early software development and as a synthesisable specification for subsequent hardware implementation.
SystemC’s C-plus-plus foundation gave it access to the extensive software-engineering ecosystem that Verilog and VHDL could not match. The language achieved industrial adoption in system-on-chip design flows where transaction-level modelling was essential, particularly in mobile-processor and consumer-electronics design.
Bluespec. Bluespec SystemVerilog, often abbreviated as BSV, originated in research by Arvind Mithal and James Hoe at the Massachusetts Institute of Technology in the late nineteen nineties. Lennart Augustsson wrote the initial implementation, called BH, as a Haskell variant. Bluespec Incorporated was co-founded in June of two thousand three by Arvind Mithal and Joe Stoy of Oxford University to commercialise the language. The language combined Verilog syntax with a guarded-atomic-action semantics that allowed the compiler to schedule rule execution into efficient hardware without manual pipelining. Bluespec targeted high-frequency design and formal verification, and it achieved industrial adoption in niche applications where the correctness-by-construction argument justified the tooling investment.
The standardisation era established Verilog and VHDL as the two industrial-standard hardware description languages, extended them with SystemVerilog and SystemC for verification and system-level modelling, and demonstrated with Bluespec that higher-level semantics could be introduced into the same syntactic family without breaking the industrial tooling.
The embedded-domain-specific-language revival began in the early twenty tens in response to several forcing functions that the standardisation-era languages did not adequately address. The first was generator-based design, where a single parameterised description should produce many concrete circuit instances depending on compile-time parameters. The second was tighter integration with software design tools and version-control workflows. The third was the desire for more expressive type systems and better error messages than Verilog and VHDL could easily provide.
The revival embeds hardware description as a domain-specific language inside a general-purpose host language, which gives the hardware designer access to the host language’s type system, build system, package ecosystem, and development tools. The trade-off is that the designer must learn the host language and its idioms in addition to the hardware-description embedding, which imposes a non-trivial learning cost.
Chisel. Chisel, the Constructing Hardware in a Scala Embedded Language, was developed by Krste Asanović’s group at the Parallel Computing Laboratory of the University of California Berkeley beginning in two thousand twelve. The core Chisel team included Asanović along with graduate students Yunsup Lee and Andrew Waterman, who also originated the RISC-V instruction set architecture in the same lab. Chisel embeds hardware description as a Scala library. The Rocket Chip generator, which produces RISC-V processor implementations, is written in Chisel, which gave the language substantial credibility in academic and industrial RISC-V design flows.
SpinalHDL. SpinalHDL was developed by Charles Papon beginning in two thousand fifteen. Like Chisel, SpinalHDL embeds hardware description as a Scala library. SpinalHDL diverged from Chisel by emphasising strong static typing and by providing a richer standard library of pre-designed hardware components. The two Scala-based languages now coexist as complementary alternatives in the same overall generator-based design space.
Amaranth. Amaranth, originally called nMigen, was developed by Catherine “whitequark” and other contributors beginning in December of two thousand eighteen, with the rename to Amaranth announced in December of two thousand twenty-one. Amaranth embeds hardware description as a Python library and uses Yosys as its synthesis backend. It succeeded Migen, Sébastien Bourdeauducq’s earlier Python-based hardware description library from two thousand seven. Amaranth targets the field-programmable-gate-array design space that open-source tooling principally addresses, and it has become the default choice for hobbyist and open-source FPGA projects in the twenty twenties.
MyHDL. MyHDL was developed by Jan Decaluwe beginning in two thousand three. MyHDL predates the broader embedded-DSL revival and uses Python for hardware description before Migen and Amaranth made that approach widespread. MyHDL converts its Python descriptions to Verilog or VHDL for synthesis, which allows the language to inter-operate with industrial toolchains without requiring the toolchains to support Python natively.
Clash. Clash was developed by Christian Baaij at Utrecht University and later Delft University of Technology across the twenty tens. Clash embeds hardware description in Haskell. The language uses Haskell’s type system and functional-programming idioms to describe combinational and sequential circuits, and compiles its Haskell descriptions to VHDL, Verilog, or SystemVerilog for industrial synthesis flows.
Chisel-adjacent and Chisel-successor languages. Several languages in the twenty tens extended or succeeded Chisel’s design pattern. FIRRTL, the Flexible Intermediate Representation for RTL, provides a common target that several front-end languages compile to before subsequent synthesis-tool consumption. Diplomacy, a Chisel library, provides compositional interconnect design that supports system-on-chip integration at the source-language level. These are not independent hardware description languages in the historical sense but component technologies in the broader Chisel design ecosystem.
The embedded-DSL revival has changed the shape of hardware description in academic and open-source contexts but has not displaced Verilog and VHDL in industrial mainstream flows. The two traditions now coexist, with industrial designers using SystemVerilog for production design work and open-source projects using Amaranth or Chisel for academic and hobbyist work.
Alongside the main hardware description language lineage, a parallel track of verification-specific languages developed across the standardisation era. Verification languages describe properties that a design must satisfy, rather than describing the design itself.
Property Specification Language, PSL. PSL was developed by Accellera and standardised as IEEE 1850 in two thousand five. The language derives from IBM’s Sugar property specification language of the late nineteen nineties and provides a compact temporal-logic syntax that formal verification tools can consume for model checking and theorem proving.
SystemVerilog Assertions, SVA. SVA provides a temporal-assertion syntax inside SystemVerilog that allows designers to embed formal properties directly in their design source. SVA has largely displaced PSL in industrial adoption because SystemVerilog was already the dominant design language when both were standardised.
Universal Verification Methodology, UVM. UVM provides a verification testbench methodology built on SystemVerilog’s object-oriented features. It is not a language in the strict sense, but a reusable class library that Accellera standardised in two thousand ten and IEEE adopted as IEEE 1800.2 in two thousand seventeen. UVM has become the industrial standard for verification-heavy design flows.
A separate track of higher-level synthesis attempted to raise the abstraction level above the register-transfer level that Verilog and VHDL principally target. High-level synthesis tools consume a sequential specification and generate a pipelined hardware implementation that implements the same functionality.
Behavioral Verilog and Behavioral VHDL. Both Verilog and VHDL support a behavioural subset that higher-level synthesis tools can consume. Synopsys and Cadence provided behavioural synthesis tools across the nineteen nineties and two thousands, though adoption remained limited because the resulting circuits were often inefficient compared to hand-designed register-transfer-level implementations.
SystemC HLS. SystemC was developed in part as a target for high-level synthesis. The Vivado HLS tool from Xilinx and the Catapult HLS tool from Siemens both consume SystemC or C-plus-plus source and generate synthesisable register-transfer-level output. Industrial adoption of these tools grew across the twenty tens but did not match the adoption of register-transfer-level design in Verilog and VHDL.
Modern high-level synthesis alternatives. Recent high-level synthesis efforts have targeted domain-specific accelerator design, where the design space is narrow enough that the tool can produce efficient hardware without manual tuning. Cornell’s Dahlia and similar academic projects demonstrate the approach for deep-learning accelerator design and scientific-computing workloads.
The design-complexity forcing function that this article opened with returns as the organising explanation for the historical sequence. Each wave of hardware description languages appeared in response to a specific abstraction gap that prior languages did not close.
The academic prototypes appeared because gate-level netlists did not scale past the medium-scale-integration boundary. The standardisation era appeared because the academic prototypes did not have sufficient tooling and industrial commitment to support production design flows. The embedded-DSL revival appeared because Verilog and VHDL did not have adequate generator-based design support or integration with modern software-engineering workflows.
The pattern repeats because Moore’s Law continued to raise the transistor count per chip across each decade of this history, and each wave addressed the abstraction gap that the prior wave had left open at the new scale. The pattern appears to be continuing into the current decade, with domain-specific accelerator design now occupying the abstraction gap that general-purpose hardware description does not efficiently close.
Several developments in the twenty twenties appear to be shaping the next wave of hardware description.
Formal-methods integration. The formal verification community has increasingly adopted hardware description languages as their target, with Coq-based and Isabelle-based hardware specification work producing verified implementations of processor cores and accelerator designs. The Kami framework and its successors represent this line of work.
Machine-learning-driven design. Large language models have begun to generate Verilog and VHDL from natural-language specifications. The quality of generated designs remains mixed as of the early twenty twenties, but the trajectory suggests that hardware description may become a compilation target for higher-level intent specifications rather than a directly-authored source language.
Open-source industrial tooling. Yosys, the open-source synthesis toolchain, has matured sufficiently to support production design flows for some field-programmable-gate-array applications. The combination of Yosys with Amaranth or Chisel provides a fully open-source hardware design toolchain that has attracted academic and hobbyist adoption and is beginning to find industrial applications in niche domains.
Domain-specific hardware description. Recent academic work has produced domain-specific hardware description languages for deep-learning accelerator design, digital signal processing, and scientific computing. These languages narrow the design space enough to enable substantially higher-level description than Verilog and VHDL can efficiently support, at the cost of generality.
Hardware description languages have followed a recognisable trajectory across five decades. Academic prototypes in the seventies established the register-transfer-level abstraction and the event-driven simulation model. Verilog and VHDL in the eighties supplied the industrial tooling that the academic prototypes could not match. SystemVerilog and SystemC in the two thousands extended the standardisation-era languages with verification and system-level modelling. The embedded-DSL revival of the twenty tens introduced generator-based design and integration with modern software-engineering workflows through Chisel, Amaranth, SpinalHDL, Clash, and related languages. Verification-specific languages developed alongside the main lineage across the standardisation era. High-level synthesis efforts attempted to raise the abstraction level above the register-transfer level with mixed industrial success.
The forcing function throughout this history has been the growth in transistor count per chip that Moore’s Law sustained across five decades. Each successive wave of hardware description languages appeared in response to the abstraction gap that the prior wave left open at the new scale of integration. The pattern appears to be continuing into the current decade, with domain-specific accelerator design, formal-methods integration, and machine-learning-driven design synthesis shaping the next wave.
The full historical record of hardware description languages is richer than this article can compactly cover, and readers who need detail on specific languages should consult the primary sources that the reference list below identifies.